# Single Cycle

We have built the complete RV32I datapath. Now we gonna design the control unit.

<figure><img src="https://733403343-files.gitbook.io/~/files/v0/b/gitbook-x-prod.appspot.com/o/spaces%2Fz6F38NLmIOefVEORubUB%2Fuploads%2FZJBdBsQGKXLOJWXHD9ZH%2Fcomplete-datapath.jpg?alt=media&#x26;token=1667c9d9-829b-4bfb-a699-c63300b893b6" alt=""><figcaption></figcaption></figure>

## Control Unit

<figure><img src="https://733403343-files.gitbook.io/~/files/v0/b/gitbook-x-prod.appspot.com/o/spaces%2Fz6F38NLmIOefVEORubUB%2Fuploads%2Fgit-blob-23965327fb37e3c22a0f926ab9b6a46d5bc991c7%2Fcontrol-truth-table.png?alt=media" alt=""><figcaption></figcaption></figure>

{% hint style="info" %}
* Some instructions are omitted, for example, `bge` and `bgeu`.
* LdSel signal is omitted.
{% endhint %}

## Timing

{% hint style="info" %}
Think of the following questions carefully. You need to find the answer on your own through your own effort.

**1. Why an instruction can be executed in single cycle in a single-cycle processor?**

**2. What properties are needed for instruction memory, data memory and register file?**

**3. What if the instruction memory or data memory or register file can only be read synchronously?**

**4. What's the possible critical path of single-cycle processor?**
{% endhint %}

<figure><img src="https://733403343-files.gitbook.io/~/files/v0/b/gitbook-x-prod.appspot.com/o/spaces%2Fz6F38NLmIOefVEORubUB%2Fuploads%2Fgit-blob-a2908b69669badb5c5f16fe2790873c49d2115be%2Fsingle-cycle-timing.jpg?alt=media" alt=""><figcaption></figcaption></figure>

Basically, each instruction comes in at its first rising clock edge and finish at its second rising clock edge (often write its result back).
