FPGA build flow

Design Reports and Logs:

• post_synth_utilization.rpt: Resource utilization report after synthesis.

• post_place_utilization.rpt: Resource utilization report after placement.

• post_route_timing_summary.rpt: Timing summary report after routing.

References

• EECS 151/251A 2024 spring fpga lab1

• Vivado Design Suite Tcl Command Reference Guide (UG835)