Get started with vivado 24.1

DEVICE: ZYNQ7000 - AX7020

Create a project

Open vivado, and then click Create Project.

Specify the project name and location. I use the breathing light circuit to demonstrate.

Select RTL Project and check Do not specify sources at this time.

Our device information is at Our device

To create the project, click Finish.

Design

Now, it's time to add our verilog design source code.

First click Create File, and then specify the File type to SystemVerilog and File name to led.

Here is led.sv. You can paste it in.

module led (
    input sys_clk,
    input rst_n,
    output reg [3:0] led);
    
    parameter PERIOD = 32'd49_999_999;
    
    reg [31:0] timer_cnt;
    
    always@(posedge sys_clk or negedge rst_n) begin
        if (!rst_n) begin
            led <= 4'd0;
            timer_cnt <= 32'd0;
        end else if (timer_cnt >= PERIOD) begin
            led <= ~led;
            timer_cnt <= 32'd0;
        end else begin
            led <= led;
            timer_cnt <= timer_cnt + 32'd1;
        end
    end
    
endmodule

Simulation

It's a good habit to write testbench for your verilog code. If you don't know how to write a testbench or you don't familiar with it, you should check the tutorials released by EDAPlayground, and here is the link.

Just name it testbench.

Here is testbench.sv. You can change the code as long as you fully understand it.

`timescale 1ns / 1ps

module testbench;

    reg clk, rst_n;
    wire [3:0] led;
    
    led #(.PERIOD(4)) dut (
        .sys_clk(clk),
        .rst_n(rst_n),
        .led(led)
        );
        
    initial begin
        clk = 0;
        rst_n = 0;
        #5 rst_n = 1;
        
        #50;
        
        rst_n = 0;
        $5 $finish;
    end
    
    always #5 clk = ~clk;
    
endmodule

First click Run Simulation, and then click Run Behavioral Simulation to run simulation.

Here is the waveform.

Maybe you need to scale the waveform down. And you can drag dut (design under test) instance to the waveform to see the signals inside the instance.

Schematic

Click Open Elaborated Design.

Click Schematic, and then you can see an intuitive diagram showing up in the editor area.

Pin planning

In I/O Ports window, set the Package Pin and I/O Std. The settings is related to our device details.

Click the upper left corner save icon to save the constrains. Just name it led.

You can see led.xdc created in your project.

Synthesis

Now run synthesis.

When synthesis completed, click Cancel. Because we need to add timing constraints first.

Timing Constraints

Click Contraints Wizard and then click Next.

Set the timing constraints and then click Skip to Finish.

Click Finish.

You can see the timing constraints in led.xdc automatically generated.

Generate Bitstream

Click Generate Bitstream.

If you haven't run implementation before, vivado will give you a hint to run implementation and you just run it.

When bitstream generation completed, check Open Hardware Manager and then click OK.

Make sure our device is connected and power on.

Click Open target and then click auto connect. If the cable driver is correctly installed, you can see our device in the hardware window.

Possible solutions to "vivado cannot find your device" (linux version):

cd to directory "/path/to/Xilinx/Vivado/<vivado-version>/data/xicom/cable_drivers/lin64/install_script/install_drivers".

change "/path/to" to the real path to Xilinx for example "/tools" or "/opt"
change "<vivado-version>" to the real vivado version for example "2024.1"
In the directory, there is a install_drivers script (same name as the directory name), run using command sudo ./install_drivers

UG973 may be useful to you.

Right click our device xc7z020_1, and then click Program Device.

Leave it the default Bitstream File and click Program.

Now, you can see the breathing light effect.