# Get started with vivado 24.1
## Create a project
Open vivado, and then click `Create Project`.
Specify the project name and location. I use the breathing light circuit to demonstrate.
Select `RTL Project` and check `Do not specify sources at this time`.
Our device information is at [Our device](https://github.com/byrzhm/build-a-riscv-chip-from-scratch/blob/main/tools/broken-reference/README.md)
To create the project, click `Finish`.
## Design
Now, it's time to add our verilog design source code.
First click `Create File`, and then specify the `File type` to `SystemVerilog` and `File name` to `led`.
Here is `led.sv`. You can paste it in.
```verilog
module led (
input sys_clk,
input rst_n,
output reg [3:0] led);
parameter PERIOD = 32'd49_999_999;
reg [31:0] timer_cnt;
always@(posedge sys_clk or negedge rst_n) begin
if (!rst_n) begin
led <= 4'd0;
timer_cnt <= 32'd0;
end else if (timer_cnt >= PERIOD) begin
led <= ~led;
timer_cnt <= 32'd0;
end else begin
led <= led;
timer_cnt <= timer_cnt + 32'd1;
end
end
endmodule
```
## Simulation
It's a good habit to write testbench for your verilog code. If you don't know how to write a testbench or you don't familiar with it, you should check the tutorials released by [EDAPlayground](https://www.edaplayground.com/), and here is the [link](https://www.youtube.com/playlist?list=PLScWdLzHpkAfbPhzz1NKHDv2clv1SgsMo).
Just name it `testbench`.
Here is `testbench.sv`. You can change the code as long as you fully understand it.
```verilog
`timescale 1ns / 1ps
module testbench;
reg clk, rst_n;
wire [3:0] led;
led #(.PERIOD(4)) dut (
.sys_clk(clk),
.rst_n(rst_n),
.led(led)
);
initial begin
clk = 0;
rst_n = 0;
#5 rst_n = 1;
#50;
rst_n = 0;
$5 $finish;
end
always #5 clk = ~clk;
endmodule
```
First click `Run Simulation`, and then click `Run Behavioral Simulation` to run simulation.
Here is the waveform.
{% hint style="info" %}
Maybe you need to scale the waveform down. And you can drag dut (design under test) instance to the waveform to see the signals inside the instance.
{% endhint %}
## Schematic
Click `Open Elaborated Design`.
Click `Schematic`, and then you can see an intuitive diagram showing up in the editor area.
## Pin planning
In `I/O Ports` window, set the `Package Pin` and `I/O Std`. The settings is related to our [device details](https://github.com/byrzhm/build-a-riscv-chip-from-scratch/blob/main/tools/broken-reference/README.md).
Click the upper left corner save icon to save the constrains. Just name it `led`.
You can see `led.xdc` created in your project.
## Synthesis
Now run synthesis.
When synthesis completed, click `Cancel`. Because we need to add timing constraints first.
## Timing Constraints
Click `Contraints Wizard` and then click `Next`.
Set the timing constraints and then click `Skip to Finish`.
Click `Finish`.
You can see the timing constraints in `led.xdc` automatically generated.
## Generate Bitstream
Click `Generate Bitstream`.
{% hint style="info" %}
If you haven't run implementation before, vivado will give you a hint to run implementation and you just run it.
{% endhint %}
When bitstream generation completed, check `Open Hardware Manager` and then click `OK`.
Make sure our device is connected and power on.
Click `Open target` and then click `auto connect`. If the cable driver is correctly installed, you can see our device in the hardware window.
{% hint style="info" %}
Possible solutions to "vivado cannot find your device" (linux version):
`cd` to directory "`/path/to/Xilinx/Vivado//data/xicom/cable_drivers/lin64/install_script/install_drivers`".
* change "/path/to" to the real path to Xilinx for example "/tools" or "/opt"
* change "\" to the real vivado version for example "2024.1"
* In the directory, there is a `install_drivers` script (same name as the directory name), run using command `sudo ./install_drivers`
[UG973](https://docs.amd.com/r/en-US/ug973-vivado-release-notes-install-license/Install-Cable-Drivers) may be useful to you.
{% endhint %}
Right click our device `xc7z020_1`, and then click `Program Device`.
Leave it the default Bitstream File and click `Program`.
Now, you can see the breathing light effect.
## References
* [Tsinghua](https://lab.cs.tsinghua.edu.cn/digital-logic-lab/doc/lab4/vivado_use/)
* [Alinx tutorial](https://www.bilibili.com/video/BV1JJ411u77d?p=2\&vd_source=571900c3ae9bbfdc988accacb2feb8be)
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