> For the complete documentation index, see [llms.txt](https://byrzhm.gitbook.io/build-a-risc-v-chip-from-scratch/llms.txt). Markdown versions of documentation pages are available by appending `.md` to page URLs; this page is available as [Markdown](https://byrzhm.gitbook.io/build-a-risc-v-chip-from-scratch/tutorial/riscv-basics.md).
# RISC-V Basics
## Complete RV32I ISA
Here is the complete RV32I ISA. We gonna implement most part of it except the gray part.
Complete RV32I ISA
{% hint style="info" %}
We are not going to handle *exceptions*.
{% endhint %}
## RISC-V Instruction Formats
The RV32I ISA can be divided into six intruction formats(R/I/S/B/U/J), as shown in the figure below.
RISC-V Instruction Formats
## "State" Required by RV32I ISA
***Processors are basically FSMs.*** Each instruction reads and updates this state during execution:
* Registers (`x0` .. `x31`)
* Program Counter (PC)
* Memory (MEM)
{% hint style="info" %}
`x0` is hardwired to 0 (i.e., always 0). Writes to `Reg[0]` are ignored.
{% endhint %}
RISC-V state elements
## Microarchitecture Organization
RISC-V state elements
## Microarchitecture
There are multiple implementations for a single instruction set architecture:
* Single-cycle
* Each instruction executes in a single clock cycle.
* Multicycle
* Each instruction is broken up into a series of shorter steps with one step per clock cycle.
* Pipelined (variant on "multicycle")
* Each instruction is broken up into a series of steps with one step per clock cycle.
* Multiple instructions execute at once by overlapping in time.
* Superscalar
* Multiple functional units to execute at once by overlapping in time.
* Out of order
* Instructions are reordered by the hardware.
{% hint style="info" %}
We will implement a single-cycle processor first, and then a pipelined one.
{% endhint %}
## References
* The RISC-V related lectures of [EECS151/251A](https://www.eecs151.org)
* The RV32I [specification](https://drive.google.com/file/d/1uviu1nH-tScFfgrovvFCrj7Omv8tFtkp/view).
