Build A RISC-V Chip From Scratch
  • Tutorial
    • Overview
    • RISC-V Basics
    • Datapath
      • R-type
      • I-type
      • S-type
      • B-type
      • U-type
      • J-type
    • Single Cycle
      • Implementation
      • More Fun
    • Pipelined
  • Interfaces
    • Graphics
      • VGA
      • HDMI
      • Draw an image using FPGA
    • Serial Interface
      • UART and FIFO
      • Echo
      • Memory Controller
  • Tools
    • Install vivado 24.1
    • Get started with vivado 24.1
    • Get started with quartus
    • FPGA build flow
    • Tcl
    • Verilog testbench
    • Open-source tools for FPGA development
      • iverilog
      • nextpnr
    • RISC-V Toolchain
      • RISC-V Toolchain Installation
      • RISC-V Toolchain Usage
  • Devices
    • Alinx AX7020
    • DE10-Stanard
  • Misc
    • Input Conditioning Circuits
    • Build A RISC-V Soft Core CPU
    • Introduction to FPGA
    • Clock Wizard
    • What is an IP core?
    • Test and Debug Soft Cores
Powered by GitBook
On this page
  • UART
  • What is UART?
  • UART receiver
  • UART transmitter
  • FIFO
  • References
  1. Interfaces
  2. Serial Interface

UART and FIFO

PreviousSerial InterfaceNextEcho

Last updated 9 months ago

UART

Baud Rate vs. Bandwidth

Baud rate always refers to symbol rate, but not always bit rate. But here a symbol is really one bit.

See

What is UART?

UART receiver

UART transmitter

FIFO

References

what is the difference between a baud rate and a bandwidth?
EECS 151/251A 2024 spring fpga lab5