Build A RISC-V Chip From Scratch
  • Tutorial
    • Overview
    • RISC-V Basics
    • Datapath
      • R-type
      • I-type
      • S-type
      • B-type
      • U-type
      • J-type
    • Single Cycle
      • Implementation
      • More Fun
    • Pipelined
  • Interfaces
    • Graphics
      • VGA
      • HDMI
      • Draw an image using FPGA
    • Serial Interface
      • UART and FIFO
      • Echo
      • Memory Controller
  • Tools
    • Install vivado 24.1
    • Get started with vivado 24.1
    • Get started with quartus
    • FPGA build flow
    • Tcl
    • Verilog testbench
    • Open-source tools for FPGA development
      • iverilog
      • nextpnr
    • RISC-V Toolchain
      • RISC-V Toolchain Installation
      • RISC-V Toolchain Usage
  • Devices
    • Alinx AX7020
    • DE10-Stanard
  • Misc
    • Input Conditioning Circuits
    • Build A RISC-V Soft Core CPU
    • Introduction to FPGA
    • Clock Wizard
    • What is an IP core?
    • Test and Debug Soft Cores
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  • Contents
  • Reading List
  1. Tutorial

Overview

NextRISC-V Basics

Last updated 7 months ago

We will build a RISC-V chip from scratch, are you ready for it? 😎

Contents

  • tutorial: build a RISC-V chip step by step, from single-cycle to pipelined

  • interfaces: serial interfaces and graphics interfaces

  • tools: provide some tools and guides that may be useful to you

  • devices: our devices documentations

  • misc: miscellaneous resources

  • If you don't familiar with fpga, check introduction to FPGA. 👈

  • You may find install vivado 24.1 and get started with vivado 24.1 useful. 👈

  • Some open-source and multiplatform tools like openFPGALoader and APIO can be alternatives to Vivado and Quartus. Basically, xilinx's and altera's FPGAs can be programmed in the same tool. 🙀

Reading List

Digital Design and Computer Architecture RISC-V Edition, by Sarah L Harris and David Harris
Computer Organization and Design RISC-V Edition, by David Patterson and John Hennessy