VGA

Last updated 9 months ago

VGA

It may be overwhelming to people who are first learning video connectors or interfaces. I highly recommend reading . This chapter provides detailed explanations and HDL code examples that are crucial for understanding VGA.

Key points

VGA signals

We need 5 signals to drive a VGA monitor.

R, G and B (red, green and blue signals)
HS and VS (horizontal and vertical synchronization)

The R, G and B are analog signals, while HS and VS are digital signals.

Signal de (data enable, not shown in picture) is occasionally necessary, but most of the time it is not.

Important parameters

640x480

1280x720

Horizontal Active Pixels

640

1280

Horizontal Front Porch

110

Horizontal Sync Width

Horizontal Back Porch

220

Horizontal Total Blanking

160

370

Horizontal Total Pixels

800

1650

Horizontal Sync Polarity

negative

positive

Vertical Active Pixels

480

720

Vertical Front Porch

Vertical Sync Width

Vertical Back Porch

Vertical Total Blanking

Vertical Total Pixels

525

750

Vertical Sync Polarity

negative

positive

Image a 640x480 @ 60Hz VGA monitor. What's the bandwith of it?

There are 640x480 pixels in one frame, and each pixel cantains 24bit RGB values. So The bandwith should be 640x480x24x60 bps, roughly 0.44Gbps. But remember we have off-screen area because of the horizontal and vertical blanking intervals (more precisely, horizontal and vertical front and back porches, horizontal and vertical synchronization). Our 640x480 frame is actually sent as an 800x525 frame. So the actual bandwith is roughly 0.6Gbps, but only %73 of it really transfers the data.

Generate VGA signals

A important concept is pixel clock, i.e., the number of pixels painted per clock. For example, a 640x480 @ 60Hz VGA monitor has pixel clock 800x525x60Hz = 25.2MHz (offscreen area is calculated as well).

Because the pixel clock is often different with the system clock, we need a pixel clock generator. We can use counter to do this, but more often we use PLL or MMCM IP cores. If we have pixel clock, then we can build hsync and vsync signals.

module simple_480p (
    input  wire logic clk_pix,   // pixel clock
    input  wire logic rst_pix,   // reset in pixel clock domain
    output      logic [9:0] sx,  // horizontal screen position
    output      logic [9:0] sy,  // vertical screen position
    output      logic hsync,     // horizontal sync
    output      logic vsync,     // vertical sync
    output      logic de         // data enable (low in blanking interval)
    );

    // horizontal timings
    parameter HA_END = 639;           // end of active pixels
    parameter HS_STA = HA_END + 16;   // sync starts after front porch
    parameter HS_END = HS_STA + 96;   // sync ends
    parameter LINE   = 799;           // last pixel on line (after back porch)

    // vertical timings
    parameter VA_END = 479;           // end of active pixels
    parameter VS_STA = VA_END + 10;   // sync starts after front porch
    parameter VS_END = VS_STA + 2;    // sync ends
    parameter SCREEN = 524;           // last line on screen (after back porch)

    always_comb begin
        hsync = ~(sx >= HS_STA && sx < HS_END);  // invert: negative polarity
        vsync = ~(sy >= VS_STA && sy < VS_END);  // invert: negative polarity
        de = (sx <= HA_END && sy <= VA_END);
    end

    // calculate horizontal and vertical screen position
    always_ff @(posedge clk_pix) begin
        if (sx == LINE) begin  // last pixel on line?
            sx <= 0;
            sy <= (sy == SCREEN) ? 0 : sy + 1;  // last line on screen?
        end else begin
            sx <= sx + 1;
        end
        if (rst_pix) begin
            sx <= 0;
            sy <= 0;
        end
    end
endmodule

We specify sx and sy as 10 bits registers. You should change it to fit your own needs, otherwise it may not show anything. Try to explain why according to the code. (hint: sx overflow)