VGA
Recommend reading
It may be overwhelming to people who are first learning video connectors or interfaces. I highly recommend reading Chapter 9.4.2 of Harris & Harris DDCA. This chapter provides detailed explanations and HDL code examples that are crucial for understanding VGA.
Key points
VGA signals
We need 5 signals to drive a VGA monitor.
R, G and B (red, green and blue signals)
HS and VS (horizontal and vertical synchronization)

The R, G and B are analog signals, while HS and VS are digital signals.
Important parameters
See more at https://projectf.io/posts/video-timings-vga-720p-1080p/.
Horizontal Active Pixels
640
1280
Horizontal Front Porch
16
110
Horizontal Sync Width
96
40
Horizontal Back Porch
48
220
Horizontal Total Blanking
160
370
Horizontal Total Pixels
800
1650
Horizontal Sync Polarity
negative
positive
Vertical Active Pixels
480
720
Vertical Front Porch
10
5
Vertical Sync Width
2
5
Vertical Back Porch
33
20
Vertical Total Blanking
45
30
Vertical Total Pixels
525
750
Vertical Sync Polarity
negative
positive


Generate VGA signals
Because the pixel clock is often different with the system clock, we need a pixel clock generator. We can use counter to do this, but more often we use PLL or MMCM IP cores. If we have pixel clock, then we can build hsync and vsync signals.
The following exmaple code demonstrate how to generate some of the important signals. (comes from simple_480.sv)
module simple_480p (
input wire logic clk_pix, // pixel clock
input wire logic rst_pix, // reset in pixel clock domain
output logic [9:0] sx, // horizontal screen position
output logic [9:0] sy, // vertical screen position
output logic hsync, // horizontal sync
output logic vsync, // vertical sync
output logic de // data enable (low in blanking interval)
);
// horizontal timings
parameter HA_END = 639; // end of active pixels
parameter HS_STA = HA_END + 16; // sync starts after front porch
parameter HS_END = HS_STA + 96; // sync ends
parameter LINE = 799; // last pixel on line (after back porch)
// vertical timings
parameter VA_END = 479; // end of active pixels
parameter VS_STA = VA_END + 10; // sync starts after front porch
parameter VS_END = VS_STA + 2; // sync ends
parameter SCREEN = 524; // last line on screen (after back porch)
always_comb begin
hsync = ~(sx >= HS_STA && sx < HS_END); // invert: negative polarity
vsync = ~(sy >= VS_STA && sy < VS_END); // invert: negative polarity
de = (sx <= HA_END && sy <= VA_END);
end
// calculate horizontal and vertical screen position
always_ff @(posedge clk_pix) begin
if (sx == LINE) begin // last pixel on line?
sx <= 0;
sy <= (sy == SCREEN) ? 0 : sy + 1; // last line on screen?
end else begin
sx <= sx + 1;
end
if (rst_pix) begin
sx <= 0;
sy <= 0;
end
end
endmodule
Top level design
Four stages:
Pixel Clock
Display Signals
Drawing Graphics
Video Output (VGA, HDMI, DisplayPort)

References
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