Build A RISC-V Chip From Scratch
  • Tutorial
    • Overview
    • RISC-V Basics
    • Datapath
      • R-type
      • I-type
      • S-type
      • B-type
      • U-type
      • J-type
    • Single Cycle
      • Implementation
      • More Fun
    • Pipelined
  • Interfaces
    • Graphics
      • VGA
      • HDMI
      • Draw an image using FPGA
    • Serial Interface
      • UART and FIFO
      • Echo
      • Memory Controller
  • Tools
    • Install vivado 24.1
    • Get started with vivado 24.1
    • Get started with quartus
    • FPGA build flow
    • Tcl
    • Verilog testbench
    • Open-source tools for FPGA development
      • iverilog
      • nextpnr
    • RISC-V Toolchain
      • RISC-V Toolchain Installation
      • RISC-V Toolchain Usage
  • Devices
    • Alinx AX7020
    • DE10-Stanard
  • Misc
    • Input Conditioning Circuits
    • Build A RISC-V Soft Core CPU
    • Introduction to FPGA
    • Clock Wizard
    • What is an IP core?
    • Test and Debug Soft Cores
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  • R-Format Instruction Layout
  • R-Format Instructions
  • Datapath
  1. Tutorial
  2. Datapath

R-type

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Last updated 7 months ago

R-Format Instruction Layout

  • opcode: partially specifies what instruction it is

    • Note: This field is equal to 0110011 for all R-format register-register arithmetic instructions

  • funct7 + funct3: combined with opcode, these two fields describe what operation to perform

  • rs1(Source Register #1): specifies register containing first operand

  • rs2: specifies second register operand

  • rd(Destination Register): specifies register which will receive result of computation

Each register field holds a 5-bit unsigned integer (0-31) corresponding to a register number (x0-x31)

R-Format Instructions

Decoding funct7 and funct3 fields to select appropriate ALU functions.

Datapath

Here is our datapath for R-format instructions.

R-type instructions