Build A RISC-V Chip From Scratch
  • Tutorial
    • Overview
    • RISC-V Basics
    • Datapath
      • R-type
      • I-type
      • S-type
      • B-type
      • U-type
      • J-type
    • Single Cycle
      • Implementation
      • More Fun
    • Pipelined
  • Interfaces
    • Graphics
      • VGA
      • HDMI
      • Draw an image using FPGA
    • Serial Interface
      • UART and FIFO
      • Echo
      • Memory Controller
  • Tools
    • Install vivado 24.1
    • Get started with vivado 24.1
    • Get started with quartus
    • FPGA build flow
    • Tcl
    • Verilog testbench
    • Open-source tools for FPGA development
      • iverilog
      • nextpnr
    • RISC-V Toolchain
      • RISC-V Toolchain Installation
      • RISC-V Toolchain Usage
  • Devices
    • Alinx AX7020
    • DE10-Stanard
  • Misc
    • Input Conditioning Circuits
    • Build A RISC-V Soft Core CPU
    • Introduction to FPGA
    • Clock Wizard
    • What is an IP core?
    • Test and Debug Soft Cores
Powered by GitBook
On this page
  • Implementation Overview
  • Basic Elements
  • PC
  • Memory
  • Register File
  • ALU
  • Immediate Generator
  • Comparator
  • Control Unit
  • Connect all the components
  • Test our implementations
  1. Tutorial
  2. Single Cycle

Implementation

PreviousSingle CycleNextMore Fun

Last updated 8 months ago

Implementation Overview

First, we will implement the basic elements, i.e., PC, memory, register file, ALU and so on. Then we will connect these basic elements together with our control unit. The control unit will be super easy to implement, because RV32I is basically a nine-bit ISA!

Basic Elements

PC

PC is just a 32-bit register.

  • Only the low bits of PC are useful, because the instruction memory is limited.

  • The low two bits of PC are always zero, how to utilize it?

Memory

To implement a single-cycle processor, we need asynchronous read instruction and data memory.

Instruction Memory

For simplicity, IMEM is not writable, i.e, it's a ROM.

Check my implementation here.

Data Memory

Data memory should be synchronous write and asynchronous read RAM.

How to support sb, sh and sw?

Check my implementation.

Register File

Our register file should be synchronous write and asynchronous read.

Remember x0 is wired to 0.

Check my implemention.

ALU

ALU should support following operations:

  • ADD: y = a + b

  • SUB: y = a - b

  • AND: y = a & b

  • OR: y = a | b

  • XOR: y = a ^ b

  • SLL: y = a << b

  • SRL: y = a >> b

  • SRA: y = $signed(a) >>> b

  • SLT: y = ($signed(a) < $signed(b)) ? 1 : 0

  • SLTU: y = (a < b) ? 1 : 0

When doing shift, only the low 5 bits of b are useful.

Here is my implementation.

Immediate Generator

My implementation goes here.

Comparator

Pretty easy and here is my implementation.

Control Unit

RV32I is basically a nine bit ISA. If you get stuck, check my implementation.

Connect all the components

It's not very hard to connect all the components. If you don't know what to do, check the complete datapath we have built.

Test our implementations

I write some very simple testbenches to test my implementations, you can see these testbench at single-cycle/sim