Build A RISC-V Chip From Scratch
  • Tutorial
    • Overview
    • RISC-V Basics
    • Datapath
      • R-type
      • I-type
      • S-type
      • B-type
      • U-type
      • J-type
    • Single Cycle
      • Implementation
      • More Fun
    • Pipelined
  • Interfaces
    • Graphics
      • VGA
      • HDMI
      • Draw an image using FPGA
    • Serial Interface
      • UART and FIFO
      • Echo
      • Memory Controller
  • Tools
    • Install vivado 24.1
    • Get started with vivado 24.1
    • Get started with quartus
    • FPGA build flow
    • Tcl
    • Verilog testbench
    • Open-source tools for FPGA development
      • iverilog
      • nextpnr
    • RISC-V Toolchain
      • RISC-V Toolchain Installation
      • RISC-V Toolchain Usage
  • Devices
    • Alinx AX7020
    • DE10-Stanard
  • Misc
    • Input Conditioning Circuits
    • Build A RISC-V Soft Core CPU
    • Introduction to FPGA
    • Clock Wizard
    • What is an IP core?
    • Test and Debug Soft Cores
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On this page
  • B-Format Instruction Layout
  • Encoding Example
  • Immediate Encoding (So Far)
  • Adding Branches to Datapath
  • Branch Comparator
  • All RISC-V Branch Instructions
  1. Tutorial
  2. Datapath

B-type

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Last updated 8 months ago

All branch instructions use the B-type instruction format.

  • E.g., BEQ x1, x2, Label

    • if x1 == x2 then pc <- pc + offset

    • offset computed by compiler/assembler and stored in the immediate field(s)

  • Branches read two registers but don't write a register (similar to stores)

B-Format Instruction Layout

  • B-format is similar to S-format, with two register sources (rs1/rs2) and a 12-bit immediate

  • The 12 immediate bits encode 13-bit signed byte offsets (low bit of offset is always zero, so no need to store it)

  • But now immediate represents values -2^12 to +2^12 - 1 in 2-byte increments

Encoding Example

In the RISC-V architecture, instructions are typically 32 bits (4 bytes) in length and are aligned on 4-byte boundaries. This means that the addresses of these instructions are multiples of 4. Consequently, the lower two bits of an instruction address are always zero.

So why branch immediates only discard the LSB not the low 2 bits?

Immediate Encoding (So Far)

Adding Branches to Datapath

Branch Comparator

All RISC-V Branch Instructions