Build A RISC-V Chip From Scratch
  • Tutorial
    • Overview
    • RISC-V Basics
    • Datapath
      • R-type
      • I-type
      • S-type
      • B-type
      • U-type
      • J-type
    • Single Cycle
      • Implementation
      • More Fun
    • Pipelined
  • Interfaces
    • Graphics
      • VGA
      • HDMI
      • Draw an image using FPGA
    • Serial Interface
      • UART and FIFO
      • Echo
      • Memory Controller
  • Tools
    • Install vivado 24.1
    • Get started with vivado 24.1
    • Get started with quartus
    • FPGA build flow
    • Tcl
    • Verilog testbench
    • Open-source tools for FPGA development
      • iverilog
      • nextpnr
    • RISC-V Toolchain
      • RISC-V Toolchain Installation
      • RISC-V Toolchain Usage
  • Devices
    • Alinx AX7020
    • DE10-Stanard
  • Misc
    • Input Conditioning Circuits
    • Build A RISC-V Soft Core CPU
    • Introduction to FPGA
    • Clock Wizard
    • What is an IP core?
    • Test and Debug Soft Cores
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RISC-V Toolchain Usage

Assembler and Disassembler

This is the whole content of test.asm

addi x1, x0, 0x1 # I-Imm
sw   x1, 2(x0)   # S-Imm
beq  x1, x0, 0x4 # B-Imm
auipc x1, 0x1000 # U-Imm
jal   x1, 0x8    # J-Imm

Use riscv64-unknown-elf-as to compile it to binary code.

riscv64-unknown-elf-as -march=rv32i test.asm -o test.out

Then use riscv64-unknown-elf-objdump to dump the binary code.

riscv64-unknown-elf-objdump -d test.out

Question: Can you explain how the instructions are encoded according to the output of riscv64-unknown-elf-objdump? Or does the output match your imagination?

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Last updated 9 months ago