Build A RISC-V Chip From Scratch
  • Tutorial
    • Overview
    • RISC-V Basics
    • Datapath
      • R-type
      • I-type
      • S-type
      • B-type
      • U-type
      • J-type
    • Single Cycle
      • Implementation
      • More Fun
    • Pipelined
  • Interfaces
    • Graphics
      • VGA
      • HDMI
      • Draw an image using FPGA
    • Serial Interface
      • UART and FIFO
      • Echo
      • Memory Controller
  • Tools
    • Install vivado 24.1
    • Get started with vivado 24.1
    • Get started with quartus
    • FPGA build flow
    • Tcl
    • Verilog testbench
    • Open-source tools for FPGA development
      • iverilog
      • nextpnr
    • RISC-V Toolchain
      • RISC-V Toolchain Installation
      • RISC-V Toolchain Usage
  • Devices
    • Alinx AX7020
    • DE10-Stanard
  • Misc
    • Input Conditioning Circuits
    • Build A RISC-V Soft Core CPU
    • Introduction to FPGA
    • Clock Wizard
    • What is an IP core?
    • Test and Debug Soft Cores
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  1. Tools
  2. Open-source tools for FPGA development

iverilog

PreviousOpen-source tools for FPGA developmentNextnextpnr

Last updated 8 months ago

Basic Usage

iverilog -o hello hello.v
vvp hello

The "iverilog" and "vvp" commands are the most important commands available to users of Icarus Verilog. The "iverilog" command is the compiler, and the "vvp" command is the simulation runtime engine.

Official Documentation

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