Build A RISC-V Chip From Scratch
  • Tutorial
    • Overview
    • RISC-V Basics
    • Datapath
      • R-type
      • I-type
      • S-type
      • B-type
      • U-type
      • J-type
    • Single Cycle
      • Implementation
      • More Fun
    • Pipelined
  • Interfaces
    • Graphics
      • VGA
      • HDMI
      • Draw an image using FPGA
    • Serial Interface
      • UART and FIFO
      • Echo
      • Memory Controller
  • Tools
    • Install vivado 24.1
    • Get started with vivado 24.1
    • Get started with quartus
    • FPGA build flow
    • Tcl
    • Verilog testbench
    • Open-source tools for FPGA development
      • iverilog
      • nextpnr
    • RISC-V Toolchain
      • RISC-V Toolchain Installation
      • RISC-V Toolchain Usage
  • Devices
    • Alinx AX7020
    • DE10-Stanard
  • Misc
    • Input Conditioning Circuits
    • Build A RISC-V Soft Core CPU
    • Introduction to FPGA
    • Clock Wizard
    • What is an IP core?
    • Test and Debug Soft Cores
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On this page
  • S-Format Instruction Layout
  • I+S Immediate Generation
  • Store Instructions
  • Adding sw to datapath
  1. Tutorial
  2. Datapath

S-type

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Last updated 8 months ago

S-type instructions are used for store.

S-Format Instruction Layout

  • Mem[Reg[rs1] + offset] <- Reg[rs2]

Immediate in two parts

  • Can't have both rs2 and immediate in same place as other instructions

  • RISC-V design decision is move low 5 bits of immediate to where rd field was in other instructions - keep rs1/rs2 fields in same place

    • register names more critical than immediate bits in hardware design

I+S Immediate Generation

  • Just need a 5-bit mux between two positions where low five bits of immediate can reside in instruction

  • Other bits in immediate are wired to fixed positions in instruction

Store Instructions

Adding sw to datapath

How to control the amount of bytes to write to memory?