S-type
S-Format Instruction Layout

Mem[Reg[rs1] + offset] <- Reg[rs2]
Immediate in two parts
Can't have both rs2 and immediate in same place as other instructions
RISC-V design decision is move low 5 bits of immediate to where rd field was in other instructions - keep rs1/rs2 fields in same place
register names more critical than immediate bits in hardware design
I+S Immediate Generation

Just need a 5-bit mux between two positions where low five bits of immediate can reside in instruction
Other bits in immediate are wired to fixed positions in instruction
Store Instructions

Adding sw
to datapath
sw
to datapath
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